Integrated circuits are in widespread use in computing devices, such as personal computers and workstations. Integrated circuits allow for a large number of transistors in various configurations to be placed in close proximity of each other to effectuate faster computing performance. A prevalent form of transistor configuration implemented in the integrated circuits are the complementary metal-oxide-semiconductor (CMOS) logic circuits, used in microprocessors, micro-controllers, random access memories and other digital logic circuits. CMOS logic circuits offer advantages over other form of logic circuits by consuming less power, dissipating less heat, as well as allowing for larger density of logic to be placed on an integrated circuit.
The use of CMOS logic, however, is also not without limitations. CMOS logic circuits are not the fastest in a given process and another logic scheme known as current mode logic is used in high speed paths. Also the CMOS logic circuits require rail-to-rail (voltage source to ground) input voltage signals to operate. By virtue of design CML circuits cannot provide rail-to-rail output signals. A current mode logic (CML) signal is normally required to be converted to a rail to rail before being provided to the CMOS logic domain. As such, a CML-to-CMOS converter is used to convert CML signals to CMOS logic domain signals.
Currently, the CML-to-CMOS converters use a two stage amplification circuit: the first stage is a differential amplifier with a current mirror load, outputting to the second stage, of a CMOS inverter, which provides additional amplification to make the CML signal swing rail to rail. This two-stage amplification design, however, is not without shortcomings, especially when applied to high speed clocking circuits.
In the first stage, for example, the use of current mirror load limits the bandwidth of the circuit because to increase amplification gain, larger resistances must be used which in turn reduces the circuit bandwidth. In the second stage, for example, poor supply noise rejection exists, leading to often unacceptable levels of supply noise induced jitter in the high speed circuit. In addition, the overall two stage amplification design suffers from relatively high latencies.